As well known in the art, a semiconductor manufactured by a semiconductor manufacturing process generally experiences a test process capable of determining whether or not the semiconductor is correctly operated according to its own characteristics. This test process for the semiconductor has been conducted by a semiconductor test system. A conventional semiconductor test system will hereinafter be described with reference to FIGS. 1 to 5.
FIG. 1 is a perspective view illustrating the conventional semiconductor test system. FIG. 2 is a block diagram illustrating a conventional semiconductor test header apparatus. FIG. 3 is a block diagram illustrating a conventional apparatus for multiplying a semiconductor test pattern signal. FIGS. 4 and 5 exemplarily illustrate signal waveforms of the conventional apparatus for multiplying the semiconductor test pattern signal.
Referring to FIG. 1, the conventional semiconductor test system includes a test head 2, a handler 3, and a HIFIX board 1. The test head 2 tests a semiconductor. The handler 3 carries out a test on a plurality of semiconductors by transferring the plurality of semiconductors, and classifies the semiconductors according to the result of the test executed by the test head 2. The HIFIX board 1 is located between the test head 2 and the handler 3, such that it establishes an electrical connection between the semiconductor and the test head 2. In other words, if the semiconductor seated in an insert on a test tray is brought into contact with the sockets on the HIFIX board 1 on the condition that the HIFIX board 1 having sockets of an (m×n) matrix is matched with a test site of the handler 3, the conventional semiconductor test system can simultaneously test (m×n) semiconductors.
In the meantime, as shown in FIG. 2, the test head 2 includes a single test head substrate and a variety of circuit elements mounted on one or both sides of the test head substrate. This test head substrate includes a Pattern Generator (PG) 10, a Pin Electronic (PE) unit 30, a control computer 5, and an interface (I/F) unit 70. The pattern generator (PG) 10 generates a predetermined test pattern signal for testing the semiconductor. The pin electronic (PE) unit 30 includes: a driver 31 for recording the test pattern signal generated from the pattern generator (PG) 10 in a Device Under Test (DUT) 50; and a comparator 33 for comparing a read signal of the test pattern read by the DUT 50 with a reference signal corresponding to characteristics of the corresponding semiconductor and outputting the result of the comparison. The control computer 5 controls the semiconductor test system. The interface (I/F) unit 70 allows the control computer 5 for controlling the semiconductor test system to interface with the test head 2.
In this case, the PE unit 30 is a circuit for directly applying current and voltage signals based on test patterns to the semiconductor contained in the DUT 50. If the test pattern generator of the PG 10 generates the test pattern signal, the driver 31 contained in the PE unit 30 records a corresponding test pattern signal in a test-objective semiconductor contained in the Ball Grid Array (BGA) type DUT 50. The recorded pattern signal is read by the DUT 50, such that the read pattern signal is outputted to the comparator 33. The comparator 33 transmits a comparison resultant signal indicating the comparison result between the read signal of the test pattern and the reference signal to the control computer 5 via the interface (I/F) unit 70. The control computer 5 analyzes a corresponding comparison signal, such that it can test whether or not the corresponding semiconductor is correctly operated according to its own characteristics.
In the meantime, the semiconductor test system may be manufactured by different manufacturing companies, such that it may be driven by a signal which may have different frequency bands according to the individual manufacturing companies. For example, if the semiconductor test system is operated by a frequency signal of 1 GHz, the test pattern signal generated from the pattern generator (PG) 10 must have the frequency of 1 GHz, and the test pattern signal of 1 GHz indicating a digital signal generated from the pattern generator (PG) 10 is converted into an analog signal of 1 GHz via the PE unit 30, such that the analog signal of 1 GHz is recorded in the DUT 50.
However, a circuit design technology for processing a high frequency signal such as the 1 GHz signal requires a high-level technology, and must consume high costs of manufacturing the circuit, resulting in the increased production costs of the semiconductor test system.
In order to solve the above-mentioned problems, the conventional semiconductor test system manufacturing companies have developed an improved apparatus for multiplying the semiconductor test pattern signal. In this improved apparatus, the PG 10 may be implemented with an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) so as to output a low-frequency test pattern signal, and the low-frequency test pattern signal is multiplied by the ASIC or FPGA end, such that the semiconductor test system can output a signal having a desired frequency band.
That is, as shown in FIG. 3, a conventional apparatus 60 for multiplying the semiconductor test pattern signal includes a first pattern generator (Pattern Generator 1: PG1) 61, a second pattern generator (Pattern Generator 2: PG2) 62, a first formatter (Formatter 1: F1) 63, a second formatter (Formatter 2: F2) 64, and an XOR logic circuit 67. The first formatter (F1) 63 combines a pattern signal received from the first pattern generator (PG1) 61 with a timing signal, and outputs the combined resultant signal. The second formatter (F2) 64 combines a pattern signal received from the second pattern generator (PG2) 62 with the other timing signal different from the above timing signal generated by the first formatter (F1) 63, and outputs the combined resultant signal. The XOR logic unit 67 performs an XOR operation on the signals received from the first and second formatters (F1 and F2) 63 and 64, and outputs the XOR-operation result to the driver 31. In this case, the timing signals generated by the first and second formatters (F1 and F2) 63 and 64 have a phase difference of 180°.
Referring to the signal waveforms of the above-mentioned multiplying apparatus 60 as shown in FIG. 4, if the first pattern generator (PG1) 61 and the second pattern generator (PG2) 62 generate the same pattern signal, the relationship between the pattern signal before the multiplication and the other pattern signal after the multiplication can be readily recognized. That is, the pattern signal D multiplied by the XOR logic circuit 67 may have an amplified frequency band, and its waveform format may be equal to those of the pattern signals generated from the first and second pattern generators (PG1 and PG2) 61 and 62. In more detail, provided that the output signals of the first and second formatter (F1 and F2) 63 and 64 have the same format and a phase difference of 180 therebetween, the XOR logic circuit 67 generates a doubled-frequency waveform having a duty ratio of 50%.
On the other hand, according to the conventional apparatus for multiplying the semiconductor test pattern signal as shown in FIG. 5, if the first pattern generator (PG1) 61 and the second pattern generator (PG2) 62 generate different pattern signals, the conventional apparatus has difficulty in estimating a shape of the pattern signal before the multiplication on the basis of the multiplied pattern signal D. In other words, if the conventional apparatus desires to alternately output a user-desired pattern signal via the first and second pattern generators (PG1 and PG2) 61 and 62, it has a disadvantage in that the first and second pattern generators (PG1 and PG2) 61 and 62 unavoidably output the same signal. If the conventional apparatus desires to output irregular signals different from each other, it must compose an arbitrary pattern program by which different pattern generators (i.e., first and second pattern generators) estimate their output values in different ways. However, if the conventional apparatus is unable to perfectly estimate the output values of the first and second pattern generators (PG1 and PG2) although the above pattern program is used, it is unable to generate the pattern of irregular signals.